Method of manufacturing semiconductor integrated circuit device, and semiconductor integrated circuit device made by its method

ABSTRACT

Mutual diffusion of impurities in a gate electrode is suppressed near a boundary between an n-channel type MISFET and a p-channel type MISFET, which adopt a polycide&#39;s dual-gate structure. Since a gate electrode of an n-channel type MISFET and a gate electrode of a p-channel type MISFET are of mutually different conductivity types, they are separated to prevent the mutual diffusion of the impurities and are electrically connected to each other via a metallic wiring formed in the following steps. In a step before a gate electrode material is patterned to separate the gate electrodes, the mutual diffusion of the impurities before forming the gate electrodes is prevented by performing no heat treatment at a temperature of 700° C. or higher.

CROSS-REFERENCE TO RELATED APPLICATION

The present application claims priority from Japanese patent applicationNo. JP 2003-157737 filed on Jun. 3, 2003, the content of which is herebyincorporated by reference into this application.

BACKGROUND OF THE INVENTION

The present invention relates to a technique for manufacturing asemiconductor integrated circuit device, and particularly to a techniqueeffectively applied to manufacture of a semiconductor integrated circuitdevice having a so-called complementary MISFET with a dual-gatestructure (Dual-gate type CMOSFET), in which a gate electrodes ofn-channel type MISFET and a gate electrode of p-channel type MISFET arecomposed of silicon films of different conductivity types.

The semiconductor device in which a circuit is composed of acomplementary MISFET has recently widely adopted a dual-gate structurein which a gate electrode of n-channel type MISFET is composed of ann-type poly-silicon film and a gate electrode of p-channel type MISFETis composed of a p-type poly-silicon film.

This is due to the following reason. Namely, in the case where both gateelectrodes of n-channel type MISFET and p-channel type MISFET arecomposed of n-type poly-silicon films similarly to conventionalsemiconductor devices, the p-channel type MISFET has a buried channelstructure and short channel effects become prominent at the time ofminiaturizing the devices, so that it is necessary to adopt thedual-gate structure even if the number of steps is increased and topromote miniaturization of the devices by suppressing the short channeleffects.

Japanese Patent Laid-Open No. 11-195713 (hereinafter “Patent Document1”), Japanese Patent Laid-Open No. 9-260509 (“Patent Document 2”), andJapanese Patent Laid-Open No. 10-50857 (“Patent Document 3”) teach apolycide's dual-gate structure in which the gate electrode of n-channeltype MISFET is composed of a laminated film of an n-type poly-siliconfilm and a tungsten silicide film and the gate electrode of p-channeltype MISFET is composed of a laminated film of a p-type poly-siliconfilm and a tungsten silicide film, and then disclose a technique inwhich respective impurities in the n-type poly-silicon film and thep-type poly-silicon film in the polycide dual-gate structure areprevented from performing mutual diffusion through the tungsten silicidefilm with large diffusion coefficient.

In Patent Document 1, the gate electrode of n-channel type MISFET andthe gate electrode of p-channel type MISFET are separated on a fielddielectric film, and a portion located above the field dielectric filmand in an insulating film covering the gate electrodes is provided witha groove, and the above-mentioned gate electrodes are connected to eachother through a conductive layer such as tungsten embedded in an insideof the groove. Meanwhile, also in Patent Documents 2 and 3, the gateelectrodes are electrically connected to each other through a conductivelayer located on the field dielectric film, but the n-type poly-siliconfilm and the p-type poly-silicon film are not separated and only thetungsten silicide film is separated on the field dielectric film.

Japanese Patent Laid-Open No. 7-161826 (“Patent Document 4”) discloses atechnique for preventing mutual diffusion of respective impurities in ap-type gate electrode and an n-type gate electrode in a CMOS deviceadopting a dual-gate structure. The forming method for a dual-gateelectrode, as disclosed in this gazette, is such that a polysilicon filmis first deposited on a silicon substrate and an aperture is formed inthe polysilicon film located on an isolation region and thereby therespective polysilicon films on a p well and an n well are separatedfrom each other. Next, boron is ion-implanted into the polysilicon filmlocated on the p well and arsenic is ion-implanted into the polysiliconfilm located on the n well, and thereafter a tungsten film is depositedon the entire surface of a substrate to connect the n-type polysiliconfilm and the p-type polysilicon film by the tungsten film.

In the n-type gate electrode and the p-type gate electrode that havebeen manufactured by the above-described method, the mutual diffusion ofthe impurities can be prevented since the n-type polysilicon film andthe p-type polysilicon film are not in direct contact with each other.

Japanese Patent Laid-Open No. 2001-210725 (“Patent Document 5”)discloses a semiconductor device of dual-gate structure in which acontact is formed in a boundary between an n-type gate electrode and ap-type gate electrode and a conductive material made of refractory metalor silicide thereof is buried in the contact.

According to the above-mentioned dual-gate structure, even when ahigh-resistance region is formed on the boundary between the n-type gateelectrode and the p-type gate electrode owing to the mutual diffusion ofthe impurities, electric connection is maintained by the conductivematerial buried in the contact, so that circuit defect in which theelectric connection between the gate electrodes is lost can beprevented.

Development of a SoC (System on Chip) in which an operation circuit, amemory circuit, a logic circuit, an analog circuit, and a RF circuit,etc. are integrated onto a single semiconductor chip has recently beenpromoted as a technique for realizing miniaturization and highperformance of the system.

In the SoC, the above-described dual-gate structure is adopted to meetthe needs of the higher performance of the system. Also, when a DRAM(Dynamic Random Access Memory) is mounted on a portion of the memorycircuit, a polycide film in which a tungsten silicide film is laminatedon an upper portion of a poly-silicon film is adopted as alow-resistance gate-electric material coping with a heat treatmentperformed at high temperature in forming a capacitor of a memory cell.

SUMMARY OF THE INVENTION

However, in-the above-described polycide's dual-gate structure combininga dual-gate structure and a polycide gate structure, the impuritiescontained in the poly-silicon film constituting a portion of the gateelectrode are mutually diffused through the upper tungsten silicidelayer, and an impurity concentration in the gate electrode disposed nearthe boundary between the n-channel type MISFET and the p-channel typeMISFET is degraded. Therefore, there arises the problem that thresholdvoltage and contact resistance between tungsten silicide and polysilicon are varied.

An object of the present invention is to provide a technique capable ofsuppressing the mutual diffusion of the impurities in the gate electrodedisposed near the boundary between the n-channel type MISFET and thep-channel type MISFET adopting a polycide's dual-gate structure.

Another object of the present invention is to provide a techniquecapable of suppressing the mutual diffusion of the impurities in thegate electrode, as described above, and of minimizing an increases in acircuit area of a logic device with memory.

The above and other objects and novel features of the present inventionwill become apparent from the description of this specification and theaccompanying drawings.

Outlines of representative ones of inventions disclosed in thisapplication will be briefly described as follows.

A method of manufacturing a logic device with memory, which adopts apolycide's dual-gate structure, according to the present inventioncomprises the following steps of (a) to (e):

(a) forming a gate dielectric film over a main surface of saidsemiconductor substrate, and thereafter forming a silicon film over saidgate dielectric film;

(b) introducing a plurality of kinds of impurities into said siliconfilm, and thereby forming a n-type silicon film in a first region ofsaid semiconductor substrate and a p-type silicon film in a secondthereof;

(c) forming, above each of said n-type silicon film and said p-typesilicon film, a conductive film containing tungsten or tungsten silicideas a main component;

(d) patterning said conductive film, said n-type silicon film, and saidp-type silicon film after said step (c), and thereby forming, in saidfirst region, a gate electrode of n-channel type MISFET which iscomposed of a laminated film of said n-type silicon film and saidconductive film, and forming, in said second region, a gate electrode ofp-channel type MISFET which is composed of a laminated film of saidp-type silicon film and said conductive film; and

(e) performing a heat treatment of said semiconductor substrate at atemperature of 700° C. or higher after said step (d).

A method of manufacturing a logic device with memory, which adopts apolycide's dual-gate structure, according to the present inventioncomprises the following steps of (a) to (f):

(a) forming a first gate dielectric film, in a first region on a mainsurface of said semiconductor substrate, and forming a second gatedielectric film larger in thickness than said first gate dielectricfilm, in a second region over said main surface;

(b) forming a silicon film over said first and second gate dielectricfilms;

(c) introducing a plurality of kinds of impurities into said siliconfilm, and thereby forming a n-type silicon film and a p-type siliconfilm over said first gate dielectric film and an n-type silicon filmover said second gate dielectric film;

(d) forming, above each of said n-type silicon film and said p-typesilicon film, a conductive film containing tungsten or tungsten silicideas a main component;

(e) by patterning said conductive film, said n-type silicon film, andsaid p-type silicon film after said step (d),

forming a gate electrode of a first n-channel type MISFET, which iscomposed of a laminated film of said n-type silicon film and saidconductive film, over said first gate dielectric film, and a gateelectrode of a first p-channel type MISFET, which is composed of alaminated film of said p-type silicon film and said conductive film, andforming, over said second gate dielectric film, a gate electrode of asecond n-channel type MISFET, which is composed of a laminated film ofsaid n-type silicon film and said conductive film, and a gate electrodesof a second p-channel type MISFET, which is composed of a laminated filmof said n-type silicon film and said conductive film; and

(f) performing a heat treatment of said semiconductor substrate at atemperature of 700° C. or higher after said step (e).

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a plan view illustrating a circuit block configuration of alogic device with memory according to one embodiment of the presentinvention.

FIG. 2 is an equivalent circuit view of a memory cell and a senseamplifier of a DRAM, which is a portion of the logic device with memoryas illustrated in FIG. 1.

FIG. 3 is an equivalent circuit view of a memory cell of a SRAM, whichis a portion of the logic device with memory as illustrated in FIG. 1.

FIG. 4 is a sectional view showing a principal portion of asemiconductor substrate in a method of manufacturing a logic device withmemory according to one embodiment of the present invention.

FIG. 5 is a sectional view showing a principal portion of asemiconductor substrate in a method of manufacturing a logic device withmemory according to one embodiment of the present invention.

FIG. 6 is a sectional view showing a principal portion of asemiconductor substrate in a method of manufacturing a logic device withmemory according to one embodiment of the present invention.

FIG. 7 is a sectional view showing a principal portion of asemiconductor substrate in a method of manufacturing a logic device withmemory according to one embodiment of the present invention.

FIG. 8 is a sectional view showing a principal portion of asemiconductor substrate in a method of manufacturing a logic device withmemory according to one embodiment of the present invention.

FIG. 9 is a sectional view showing a principal portion of asemiconductor substrate in a method of manufacturing a logic device withmemory according to one embodiment of the present invention.

FIG. 10 is a sectional view showing a principal portion of asemiconductor substrate in a method of manufacturing a logic device withmemory according to one embodiment of the present invention.

FIG. 11 is a sectional view showing a principal portion of asemiconductor substrate in a method of manufacturing a logic device withmemory according to one embodiment of the present invention.

FIG. 12 is a sectional view showing a principal portion of asemiconductor substrate in a method of manufacturing a logic device withmemory according to one embodiment of the present invention.

FIG. 13 is a sectional view showing a principal portion of asemiconductor substrate in a method of manufacturing a logic device withmemory according to one embodiment of the present invention.

FIG. 14 is a sectional view showing a principal portion of asemiconductor substrate in a method of manufacturing a logic device withmemory according to one embodiment of the present invention.

FIG. 15 is a sectional view showing a principal portion of asemiconductor substrate in a method of manufacturing a logic device withmemory according to one embodiment of the present invention.

FIG. 16 is a sectional view showing a principal portion of asemiconductor substrate in a method of manufacturing a logic device withmemory according to one embodiment of the present invention.

FIG. 17 is a sectional view showing a principal portion of asemiconductor substrate in a method of manufacturing a logic device withmemory according to one embodiment of the present invention.

FIG. 18 is a sectional view showing a principal portion of asemiconductor substrate in a method of manufacturing a logic device withmemory according to one embodiment of the present invention.

FIG. 19 is a sectional view showing a principal portion of asemiconductor substrate in a method of manufacturing a logic device withmemory according to one embodiment of the present invention.

FIG. 20 is a sectional view showing a principal portion of asemiconductor substrate in a method of manufacturing a logic device withmemory according to one embodiment of the present invention.

FIG. 21 is a sectional view showing a principal portion of asemiconductor substrate in a method of manufacturing a logic device withmemory according to one embodiment of the present invention.

FIG. 22 is a sectional view showing a principal portion of asemiconductor substrate in a method of manufacturing a logic device withmemory according to one embodiment of the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Hereinafter, an embodiment of the present invention will be detailedbased on the drawings. Note that members having the same function aredenoted by the same reference symbol throughout all the drawings forexplaining the embodiment and the repetitive description thereof will beomitted.

The present embodiment is one applied to a manufacturing process of alogic device with memory, in which a logic circuit such as a centralprocessing unit (CPU) and an analog circuit, a memory circuit such as aDRAM, SRAM, or ROM, an input/output (I/O) circuit, and a power supplycircuit are, for example, integrated onto a main surface of a singlesemiconductor chip lA as illustrated in FIG. 1.

The logic circuit, the input/output (I/O) circuit, and the power circuitare configured by an n-channel type MISFET, a p-channel type MISFET, andwirings for connecting them.

In the memory circuit, the DRAM comprises: a memory array constituted bya plurality of memory cells; a memory array associate circuit (senseamplifier or sub word driver etc.) arranged on a periphery of the memoryarray and directly controlling the memory array; and a peripheralcircuit controlling the memory array associate circuit.

As illustrated in FIG. 2, each memory cell (MC) of the DRAM comprises:an n-channel type selecting MISFET (Qs) disposed at an intersectionbetween a bit-line pair (BLT and BLB); and a capacitor (C) seriallyconnected to the selecting MISFET (Qs). A sense amplifier (SA) isdisposed in a bit-line direction of the memory array, and a sub worddriver (not shown) is disposed in a word-line direction. The memoryarray associate circuit including the sense amplifier (SA) and the subword driver and the peripheral circuit, such as an input/output circuitand a power supply circuit, for controlling the memory array associatecircuit is composed of the n-channel type MISFETs and the p-channel typeMISFETs, respectively. For example, the sense amplifier (SA) asillustrated in FIG. 2 is composed of a flip-flop circuit constituted bytwo n-channel type MISFETs (Qn₁ and Qn₂) and two p-channel type MISFETs(Qp₃ and Qp₄), thereby amplifying and outputting minute signals that areread from the memory cell (MC) selected in the memory array to thebit-line pair (BLT and BLB).

The SRAM and the ROM are each composed of a memory array and aperipheral circuit. Each memory cell of the SRAM is composed of ann-channel type MISFET and a p-channel type MISFET, and the peripheralcircuit is composed of an n-channel type MISFET and a p-channel typeMISFET. Further, each memory cell of the ROM is composed of an n-channeltype MISFET while the peripheral circuit is composed of an n-channeltype MISFET and a p-channel type MISFET.

As illustrated in FIG. 3, the memory cell (MC) in the SRAM is composedof a pair of MISFETs (Qd₁ and Qd₂) for driver, a pair of MISFETs (Qp₁and QP₂) for load, and a pair of MISFETs (Qt₁ and Qt₂) for transfer, allof which is disposed at the intersection between the bit-line pair (BLTand BLB) and the word line (WL). The MISFETs for driver (Qd₁ and Qd₂)and the MISFETs for transfer (Qt₁ and Qt₂) are composed of n-channeltype MISFETs while the MISFETs for load (QP₁ and QP₂) are composed of ap-channel type MISFET.

From among the above six MISFETs constituting the memory cell (MC) inthe SRAM, the MISFET for driver (Qd₁) and the MISFET for load (QP₁)constitute a first inverter (INV₁), and the MISFET for driver (Qd₂) andthe MISFET for load (QP₂) constitute a second inverter (INV₂). The pairof inverters (INV₁ and INV₂) is cross-linked in the memory cell (MC)through a pair of local wirings (LI and LI), whereby a flip-flop circuitis composed as an information accumulating portion for storing somepieces of information corresponding to 1 bit.

From among the n-channel type MISFET and the p-channel type MISFETconstituting the above-described logic device with memory, the gateelectrode of the n-channel type MISFET has a polycide structure in whicha tungsten silicide film is laminated on an upper portion of an n-typepoly-silicon film. Meanwhile, the gate electrode of the p-channel typeMISFET has a polycide structure in which a tungsten silicide film islaminated on an upper portion of a p-type poly-silicon film. That is,the logic device with memory has a polycide's dual-gate structure.

Next, a method of manufacturing the above-mentioned logic device withmemory will be explained with reference to FIGS. 4 to 19.

As illustrated in FIG. 4, in accordance with normal manufacturingmethods, grooves are formed on a main surface of a substrate 1 made ofp-type monocrystal silicon, and then an oxide silicon film 3 is buriedin the interior thereof to form isolation grooves 2. Next, phosphor (P)is ion-implanted into one portion of the main surface of the substrate 1and B (boron) is ion-implanted into the other portion. Thereafter, thesubstrate 1 is thermally treated to diffuse their impurities (B and P),whereby p-type wells 4 and n-type wells 5 are formed.

A left-hand side portion in FIG. 4 is a sectional view illustrating aportion of the memory array of the DRAM, a central portion is asectional view illustrating a portion of the memory array associatecircuit (for example, a sense amplifier) adjacent to the memory array,and a right-hand side portion is a sectional view illustrating a portionof the memory array of the SRAM (hereinafter, the other drawings is alsosimilar thereto).

Next, impurities for controlling threshold voltage of the MISFET areion-implanted into the respective surfaces of the p-type well 4 and then-type well 5. Thereafter, the substrate 1 is thermally oxidized to forma gate oxide film 6 having a thickness of approximately 3 to 4 nm on thesurface thereof, as illustrated in FIG. 5. Subsequently, the gate oxidefilms 6 of a memory array region and a sense amplifier region of theDRAM are covered with a photoresist film 40, and the gate oxide film 6of a memory array region in the SRAM is removed by using hydrofluoricacid.

Next, after removing the photoresist film 40, the substrate 1 isthermally oxidized once again, as illustrated in FIG. 6, whereby a thingate oxide film 6b having a thickness of approximately 3 nm is formed onthe memory array region of the SRAM. Also, By performing this thermaloxidation, since the gate oxide films 6 of the memory array region andthe sense amplifier region in the DRAM re-grow, a thick gate oxide film6 a having a thickness of approximately 6 to 7 nm is formed in theseregions.

Thus, in the DRAM from the viewpoint of securing some signal amount forthe memory cell, since relatively high voltage needs to be applied tothe gate electrode of the selecting MISFET, the thick gate oxide film 6a is formed in the memory array region, whereby withstand pressure issecured therein.

Further, the memory array associate circuit such as the sense amplifierand the sub word driver needs to array elements with a high density.Therefore, when the gate electrode of n-channel type MISFET and the gateelectrode of p-channel type MISFET are connected, it is desirable todirectly connect the gate electrodes without separating them from eachother from the viewpoint of reducing a wiring density. However, in thiscase, if a n-type poly-silicon film is used for the gate electrode ofn-channel type MISFET and the a p-type poly-silicon film is used for thegate electrode of p-channel type MISFET, the mutual diffusion of theimpurities occurs at a portion where the n-type poly-silicon film andthe p-type poly-silicon film are in direct contact with each other,whereby the threshold voltage or contact resistance of the MISFET isvaried.

Thus, in the present embodiment, the memory array associate circuit ofthe DRAM, such as the sense amplifier or sub word driver, in which theelements are disposed with the high density uses a n-type poly-siliconfilm as each of the gate electrode of n-channel type MISFET and the gateelectrode of p-channel type MISFET, thereby avoiding adverse effectsowing to the mutual diffusion of the impurities. Meanwhile, in thiscase, since the p-channel type MISFET become of a buried channel type,the short channel effects become apparent. Therefore, the thick gateoxide film 6 a is formed in a region of the memory array associatecircuit, whereby the short channel effects are suppressed.

Further, in the present embodiment, the thick gate oxide film 6 a isformed in a circuit region where a gate dielectric film with highwithstand pressure is required similarly to the power supply circuit orinput/output circuit. Meanwhile, in the memory array of the SRAM orlogic circuit that need to give priority to miniaturization and highperformance of the elements, the thin gate oxide film 6 b is formed andthe dual-gate structure is adopted.

Next, as illustrated in FIG. 7, after depositing a poly-silicon film 7onto the substrate 1 by a CVD method, the poly-silicon film 7 in ap-channel type MISFET forming region (n-type well 5) in the memory arrayregion of the SRAM is covered with a photoresist film 41, and P(phosphor) is ion-implanted into the poly-silicon film 7 in an n-channeltype MISFET forming region (p-type wells 4) of the SRAM, a memory arrayregion of the DRAM, and a memory array associate circuit forming region,whereby an n-type poly-silicon film 7 n is formed. Note that anamorphous silicon film may is used instead of the above-mentionedpoly-silicon film 7.

Next, after removing the photoresist film 41, as illustrated in FIG. 8,the n-channel type MISFET forming region (p-type well 4) in the memoryarray region in the SRAM, the memory array region of the DRAM, and thememory array associate circuit region are covered with a photoresistfilm 42, and B(boron) is ion-implanted into the poly-silicon film 7 inthe p-channel type MISFET forming region (n-type wells 5) in the memoryarray region in the SRAM, whereby a p-type poly-silicon film 7 p isformed.

Next, after removing the photoresist film 42, as illustrated in FIG. 9,a W (tungsten) silicide film 8 is deposited by a spattering method onrespective upper portions of the n-type poly-silicon film 7 n and thep-type poly-silicon film 7 p, and a silicon nitride film 9 is furtherformed thereon by the CVD method.

The conductive film on each upper portion of the poly-silicon films (7 nand 7 p) may be made of W (tungsten) instead of W silicide. In thiscase, to prevent occurrence of contact reactions between thepoly-silicon films (7 n and 7 p) and the W film, a barrier layer such asWN (tungsten nitride) may be provided between both films. Also, thedielectric film on an upper portion of the W silicide film 8 may becomposed of a laminated film of a silicon oxide film and a siliconnitride film instead of the silicon nitride film 9.

In this manner, the logic device with memory according to the presentembodiment adopts a policide structure in which W silicide is laminatedonto poly-silicon as a material for forming a low resistance gateelectrode that can cope with a high-temperature heat treatment during amanufacturing process, for example, the high-temperature heat treatmentin forming a capacitor of the memory cell of the DRAM as describedlater.

Next, as illustrated in FIG. 10, a photoresist film 43 is formed on thesilicon nitride film 9, and the silicon nitride film 9 is patterned tohave the same planar shape as that of the gate electrode by dry etchingusing the photoresist film 43 as a mask.

After removing the photoresist film 43, as illustrated in FIG. 11, the Wsilicide film 8, the n-type poly-silicon film 7 n, and the p-typepoly-silicon film 7 p are patterned by the dry etching using the siliconnitride film 9 as a mask. By doing so, gate electrodes 10 n (word linesWL) of the selecting MISFET (Qs) are formed in the memory array regionof the DRAM, and respective gate electrodes 10 n and 10 n of then-channel type MISFET and the p-channel type MISFET which constitute thesense amplifier (SA) are formed in the memory array associate region.Also, respective gate electrodes 10 n and 10 n of the MISFET for driver(Qd) and the MISFET for transfer (Qt), and gate electrode 10 p of theMISFET for load (Qp) are formed in the memory array region of the SRAM.Note that only the respective gate electrodes 10 n and 10 n of the pairof MISFETs for driver (Qd₁ and Qd₂) and one gate electrode 10 p of thepair of MISFET for load (QP₁ and QP₂) are illustrated in this Figure.

FIG. 12 is a sectional view along an extending direction of the gateelectrodes 10 n and 10 p formed respectively in the memory array regionof the DRAM, the memory array associate circuit region, and the memoryarray region of the SRAM.

As illustrated in this Figure, in the sense amplifier (SA) of the DRAM,when the gate electrode 10 n of the n-channel type MISFET and the gateelectrode 10 n of the p-channel type MISFET are to be connected, bothelectrodes are directly connected without interposing any metallicwirings (central portion in the Figure). In this case, since bothconductivity types of the gate electrode 10 n of the n-channel typeMISFET and the gate electrode 10 p of the p-channel type MISFET are of ntypes, the mutual diffusion of the impurities is out of the question.

Meanwhile, in the case of the memory cell of the SRAM, the conductivitytypes of the gate electrode 10 n of the MISFET for driver (Qd) and thegate electrode 10 p of MISFET for load (Qp) are different from eachother. Therefore, both are separated (right-hand side in the Figure) toprevent the mutual diffusion of impurities, and both electrodes areelectrically connected via a metallic wiring formed in the followingsteps.

When the dry etching is performed to form the above-described gateelectrodes 10 n and 10 p, lower portions of respective sidewalls of thegate electrodes 10 n and 10 p and the gate oxide films 6 a and 6 b inthe peripheral region are also cut off to some extent and the thicknessof the films is reduced, whereby there arises the problem such asdegradation in gate withstanding pressure if such a situation remainsunchanged.

Therefore, by performing a heat treatment (re-oxidation process) of thesubstrate 1 after the above-described dry etching, the thinned gatedielectric films 6 a and 6 b are thickened. Such a re-oxidation processis performed by performing the heat treatment of the substrate 1 in areduction atmosphere of, for example, 800° C. containing a mixed gas of90% hydrogen and 10% vapor.

Since the above-described heat treatment at high temperature isperformed in a step after the gate electrodes 10 n and lop of mutuallydifferent conductivity types have been separated, no mutual diffusion ofimpurities is generated. In this manner, no heat treatment at hightemperature (for example, 700° C. or more) is performed in the stepsbefore the gate electrodes 10 n and 10 p of mutually differentconductivity types are separated, and the heat treatment at hightemperature is performed in the step after the gate electrodes 10 n and10 p of mutually different conductivity types have been separated.Therefore, it is possible to certainly prevent the mutual diffusion ofimpurities that can be caused among the gate electrodes 10 n and 10 p ofmutually different conductivity types.

Next, as illustrated in FIG. 13, As (arsenic) is ion-implanted into thep-type wells 4 to form n⁻-type semiconductor regions 13, and B (boron)is ion-implanted into the n-type wells 5 to form p⁻-type semiconductorregions 14. The n⁻-type semiconductor region 13 formed in the memoryarray of the DRAM constitutes source and drain regions of the selectingMISFET (Qs). In other words, the selecting MISFETs (Qs) are formed inthe memory array region of the DRAM through the steps performed so far.

Meanwhile, the n⁻-type semiconductor region 13 and the p⁻-typesemiconductor region 14 formed in the memory array associate circuitregion of the DRAM are low-density semiconductor regions for making then-channel type MISFET and the p-channel type MISFET be of a LDD (LightlyDoped Drain) structure.

The n-type semiconductor region 13 of the n-channel type MISFET and thep-type semiconductor region 14 of the p-channel MISFET that are formedin the memory array region of the SRAM are high-density semiconductorregions in which extremely shallow junction is made for suppressing theshort channel effects and for securing drain currents.

Next, as illustrated in FIG. 14, after depositing a silicon nitride film15 over the substrate 1 through the CVD method, the silicon nitride film15 in the memory array associate circuit region of the DRAM and in thememory array region of the SRAM is anisotropically etched, whereby sidewall spacers 15 s are formed on sidewalls of the gate electrodes 10 nand 10 p in these regions. Next, As (arsenic) or P (phosphor) ision-implanted into the p-type wells 4 of the memory array associatecircuit region in the DRAM and of the memory array region in the SRAM,and B (boron) is ion-implanted into the n-type wells 5 of these regions.Further, the substrate 1 is thermally treated at a temperature ofapproximately 900 to 1000° C. to diffuse the above-mentioned impurities,whereby a n⁺-type semiconductor regions (source and drain) 16 of then-channel type MISFET are formed in the p-type wells 4 in theabove-mentioned regions and a p⁺-type semiconductor region (source anddrain) 17 of the p-channel type MISFET is formed in the n-type well 5.The above-described high-temperature heat treatment is performed in astep after the gate electrodes 10 n and 10 p of mutually differentconductivity types have been separated, so that no mutual diffusion ofimpurities is caused.

By the steps performed so far, the n-channel type MISFET (Qn) and thep-channel type MISFET (Qp) constituting the sense amplifier (SA) areformed in the memory array associate circuit region of the DRAM, and then-channel type MISFET for driver (Qd), a MISFET for transfer (Qt) (notshown), and the p-channel type MISFET for load (Qp) are formed in thememory array region of the SRAM.

Next, as illustrated in FIG. 15, a silicon oxide film 18 is depositedover the substrate 1 through the CVD method and then contact holes 19are formed on an upper portion of the source or drain (n--typesemiconductor region 13) disposed in the memory array region of theDRAM. Thereafter, plugs 20 each formed of an n-type poly-silicon filmare buried inside the contact holes 19.

Then, as illustrated in FIG. 16, after depositing a silicon oxide film21 on the silicon oxide film 18 through the CVD method, a through hole22 is formed on the plugs 20 formed in the memory array region of theDRAM, and contact holes 23 are formed on the source and drain (n⁺-typesemiconductor region 16 and p⁺-type semiconductor region 17) formed inthe memory array associate circuit region, and contact holes 24 areformed on the source and drain (n⁺-type semiconductor region 16 andp⁺-type semiconductor region 17) formed in the memory array region ofthe SRAM and above the gate electrodes 10 n. Then, plugs 25 formed of,for example, a laminated film of a titanium nitride film (TiN) and a Wfilm are buried into respective interiors of the through holes 22 andthe contact holes 23 and 24.

Next, as illustrated in FIGS. 17 and 18 (sectional view along anextending direction of the gate electrodes 10 n and 10 p), by patterningthe W film deposited on the silicon oxide film 21 through the spatteringmethod, a bit line BL is formed in the memory array region of the DRAM,wirings 30 to 32 and 36 are formed in the memory array associate circuitregion and wirings 33 to 35 and 37 as well as a local wiring LI areformed in the memory array region of the SRAM. As illustrated in FIG.18, since the gate electrodes 10 n and 10 p in the memory array regionof the SRAM are separated from each other, the electrodes are connectedthrough the wiring 37 at a portion needing to connect these electrodes.

Note that, the plugs 25 have been buried into the contact holes 24,which are disposed above the source and drain (n⁺-type semiconductorregion 16 and p⁺-type semiconductor region 17) in the memory arrayregion of the SRAM and on the gate electrode 10 n in the above-mentionedexample. However, for example, the following configuration may be alsoadopted: as shown in FIG. 19, the contact holes 24 and the plugs 25 arenot formed on the source and drain (n⁺-type semiconductor region 16 andp⁺-type semiconductor region 17) and on the gate electrodes 10 n in thestep as illustrated in FIG. 16; as shown in FIG. 20, a contact hole 26is formed above the source and drain (n⁺-type semiconductor region 16and p⁺-type semiconductor region 17) and the gate electrode 10 n afterthe step as illustrated in FIG. 16; and then, as shown in FIG. 21, thelocal wiring. LI formed in the steps as illustrated in FIGS. 17 and 18is directly connected to the source and drain (n⁺-type semiconductorregion 16 and p⁺-type semiconductor region 17) and the gate electrode 10n.

Thereafter, as illustrated in FIG. 22, capacitors C, each of whichcomprises a lower electrode 50, a capacitive dielectric film 51, and anupper electrode 52, are formed in the memory array region of the DRAM,and then wirings 55 to 58 to be a second layer are formed on an upperlayer of the capacitors C. A lower electrode 50 of each capacitor C iscomposed of a n-type poly-silicon film deposited by, for example, theCVD method, and an upper electrode 52 thereof is composed of a titaniumnitride film deposited by the spattering and CVD methods. The capacitivedielectric film 51 is formed by: depositing a tantalum oxide film on thelower electrode 50 through the CVD method; and then performing a heattreatment of the tantalum oxide film at approximately 700 to 800° C. Thewirings 55 to 58 to be the second layer are formed by patterning analuminum (Al) alloy film deposited onto the silicon oxide film 59covering the capacitors C through the spattering method.

In the foregoing, the invention made by the present inventors has beenconcretely described based on the embodiment. However, needless to say,the present invention is not limited to the above-mentioned embodimentand can be variously modified and altered without departing from thegist thereof.

In the above-mentioned embodiment, the case where the gate electrode ofn-channel type MISFET and the gate electrode of p-channel type MISFETthat constitute the memory array associate circuit of the DRAM are ofthe same conductivity type has been described. However, if it is desiredthat the short channel effects of these MISFETs are effectivelysuppressed, a thin gate oxide film and a dual-gate structure may beadopted similarly to the memory array of the SRAM or the logic circuitof the MISFET.

In the above-mentioned embodiment, the present invention is applied tothe case where the manufacturing process of the logic device with memoryhas been described. However, the present invention is not limited tothis and can be widely applied to the manufacturing process of thedevice adopting a polycide's dual-gate structure.

Effects obtained from representative ones of the inventions disclosed bythis application will be briefly described as follows.

In the device adopting the polycide's dual-gate structure, it ispossible to certainly suppress the mutual diffusion of the impurities inthe gate electrodes disposed near the boundary between the n-channeltype MISFET and the p-channel type MISFET.

1. A method of manufacturing a semiconductor integrated circuit device,including n-channel type and a p-channel type MISFETs over asemiconductor substrate, the method comprising the steps of: (a) forminga gate dielectric film over a main surface of-said semiconductorsubstrate, and thereafter forming a silicon film over said gatedielectric film; (b) introducing a plurality of kinds of impurities intosaid silicon film, and thereby defining one portion of said silicon filmas a n-type silicon film and the other portion as a p-type silicon film;(c) forming, above each of said n-type silicon film and said p-typesilicon film, a conductive film including metal as a main component; (d)patterning said conductive film, said n-type silicon film, and saidp-type silicon film after said step (c), and thereby forming a gateelectrode of n-channel type MISFET, comprised of a laminated film ofsaid n-type silicon film and said conductive film, and forming a gateelectrode of p-channel type MISFET, comprised of a laminated film ofsaid p-type silicon film and said conductive film; and (e) performing aheat treatment of said semiconductor substrate at a temperature of 700°C. or higher after said step (d), wherein a circuit is formed over thesemiconductor substrate includes a memory circuit of a Dynamic RandomAccess Memory and a processor, the memory circuit has a memory cell ofsaid Dynamic Random Access Memory including a said n-channel typeMISFET, and the processor includes a said n-channel type MISFET and asaid p-channel type MISFET. 2-18. (canceled)
 19. The method according toclaim 1, further comprising the steps of: after said step (e), (f)forming a dielectric film over said semiconductor substrate so as tocover said gate electrodes, and forming a connection hole in saiddielectric film above said gate electrodes; and (g) forming a wiringabove said dielectric film, and electrically connecting said wiring andsaid gate electrodes through said connection hole.
 20. The methodaccording to claim 1, wherein said wiring includes a wiring forelectrically connecting said gate electrode of n-channel type MISFET andsaid gate electrode of p-channel type MISFET.
 21. The method accordingto claim 1, further comprising the step of: after said step (d) andbefore said step (e), introducing a plurality of kinds of impuritiesinto said semiconductor substrate, and thereby forming source and drainregions of said n-channel type MISFET and source and drain regions ofsaid p-channel type MISFET.
 22. The method according to claim 1, furthercomprising the step of: after said step (c) and before said step (d),performing a heat treatment of said semiconductor substrate at atemperature of 700° C. or lower.
 23. The method according to claim 1,wherein said conductive film includes a tungsten-nitride film and atungsten film formed over said tungsten-nitride film.